High-speed digital communication networks over copper and optical fiber are used in many network communication and digital storage applications. Ethernet and Fiber Channel are two widely used communication protocols, and the protocols continue to evolve in response to increasing demand for higher bandwidth in digital communication systems.
The Ethernet protocol may provide collision detection and carrier sensing in the physical layer of the OSI protocol model. The physical layer, layer 1, is responsible for handling all electrical, optical, opto-electrical and mechanical requirements for interfacing to the communication media. Notably, the physical layer may facilitate the transfer of electrical signals representing an information bitstream. The physical layer may also provide services such as, for example, encoding, decoding, synchronization, clock data recovery, and transmission and reception of bit streams. Gigabit Ethernet (GbE), which initially found application in gigabit servers, is becoming widespread in personal computers, laptops, and switches, thereby providing the necessary infrastructure for handling data traffic for PCs and servers.
As the demand for higher data rates and bandwidth continues to increase, equipment vendors are employing new design techniques for manufacturing network layer 1 equipment capable of handling these increased data rates. However, the equipment vendors are also trying to limit cost rise associated with the newer equipment, if not reduce the cost, with respect to the previous generation of equipment. Chip real estate and printed circuit board (PCB) real estate are generally expensive.
Traditionally, network equipment vendors have used memory external to a processor in which to store boot code for the processor. The external memory, which may be at least one memory chip, may incur further expenses to the manufacturer in addition to a cost of the memory chip. For example, the additional cost may be due to the additional printed circuit board real estate required for the chip, and/or the increased complexity for layout of the signal traces from the memory chip to the processor, and other chips to which the memory chip may be coupled.
Accordingly, boot code may be stored in a ROM section of a processor chip. In this manner, an additional large ROM chip or NVRAM chip may not be needed to store boot code for the processor chip. However, for these cases in which modification to the code in the ROM is desired, executable code may be stored in a small NVRAM. However, depending on the size of the executable code, it may be necessary to increase the size of the NVRAM. As the size of the NVRAM increases, the cost associated with the NVRAM may increase due to the chip cost, the additional real estate needed, and the interconnect cost if more pins are required for the larger NVRAM.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with some aspects of the present invention as set forth in the remainder of the present application with reference to the drawings.